RBS=EMPTY_NO_MESSAGE_IS, TS=IDLE_THE_CAN_CONTRO, ES=OK_BOTH_ERROR_COUNT, RS=IDLE_THE_CAN_CONTRO, DOS=ABSENT_NO_DATA_OVER, BS=BUS_ON_THE_CAN_CONT, TCS=INCOMPLETE_AT_LEAST, TBS=LOCKED_AT_LEAST_ONE
Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1.
| RBS | Receive Buffer Status. After reading all messages and releasing their memory space with the command ‘Release Receive Buffer,’ this bit is cleared. 0 (EMPTY_NO_MESSAGE_IS): Empty. No message is available. 1 (FULL_AT_LEAST_ONE_C): Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available. |
| DOS | Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled. 0 (ABSENT_NO_DATA_OVER): Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset). 1 (OVERRUN_A_MESSAGE_W): Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer). |
| TBS | Transmit Buffer Status. 0 (LOCKED_AT_LEAST_ONE): Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s). 1 (RELEASED_ALL_THREE_): Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. |
| TCS | Transmit Complete Status. The Transmission Complete Status bit is set ‘0’ (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set ‘1’ at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain ‘0’ until all messages are transmitted successfully. 0 (INCOMPLETE_AT_LEAST): Incomplete. At least one requested transmission has not been successfully completed yet. 1 (COMPLETE_ALL_REQUES): Complete. All requested transmission(s) has (have) been successfully completed. |
| RS | Receive Status. If both the Receive Status and the Transmit Status bits are ‘0’ (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. 0 (IDLE_THE_CAN_CONTRO): Idle. The CAN controller is idle. 1 (RECEIVE_THE_CAN_CON): Receive. The CAN controller is receiving a message. |
| TS | Transmit Status. If both the Receive Status and the Transmit Status bits are ‘0’ (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. 0 (IDLE_THE_CAN_CONTRO): Idle. The CAN controller is idle. 1 (TRANSMIT_THE_CAN_CO): Transmit. The CAN controller is sending a message. |
| ES | Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018). 0 (OK_BOTH_ERROR_COUNT): OK. Both error counters are below the Error Warning Limit. 1 (ERROR_ONE_OR_BOTH_O): Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register. |
| BS | Bus Status. Mode bit ‘1’ (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to ‘127’, and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set ‘0’ (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery. 0 (BUS_ON_THE_CAN_CONT): Bus-on. The CAN Controller is involved in bus activities 1 (BUS_OFF_THE_CAN_CON): Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| RXERR | The current value of the Rx Error Counter (an 8-bit value). |
| TXERR | The current value of the Tx Error Counter (an 8-bit value). |